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| k70p256m120sf3 k70 sub-family supports the following: mk70fx512vmj12, mk70fn1m0vmj12 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 120 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 1024 kb program flash memory on non- flexmemory devices C up to 512 kb program flash memory on flexmemory devices C up to 512 kb flexnvm on flexmemory devices C 16 kb flexram on flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface C ddr controller interface C nand flash controller interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C multiple low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 32-channel dma controller, supporting up to 128 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C tamper detect and secure storage C hardware random-number generator C hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms C 128-bit unique identification (id) number per chip ? human-machine interface C graphic lcd controller C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C four 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C two 12-bit dacs C four analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C two 8-channel motor control/general purpose/pwm timers C two 2-channel quadrature decoder/general purpose timers C ieee 1588 timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock freescale semiconductor document number: k70p256m120sf3 data sheet: technical data rev. 4, 10/2012 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012 freescale semiconductor, inc.
? communication interfaces ethernet controller with mii and rmii interface to external phy and hardware ieee 1588 capability usb high-/full-/low-speed on-the-go controller with ulpi interface usb full-/low-speed on-the-go controller with on-chip transceiver two controller area network (can) modules three spi modules two i2c modules six uart modules secure digital host controller (sdhc) two i2s modules k70 sub-family data sheet, rev. 4, 10/2012. 2 freescale semiconductor, inc. table of contents 1 ordering parts ........................................................................... 5 1.1 determining valid orderable parts...................................... 5 2 part identification ...................................................................... 5 2.1 description......................................................................... 5 2.2 format ............................................................................... 5 2.3 fields ................................................................................. 5 2.4 example ............................................................................ 6 3 terminology and guidelines ...................................................... 6 3.1 definition: operating requirement...................................... 6 3.2 definition: operating behavior ........................................... 6 3.3 definition: attribute ............................................................ 7 3.4 definition: rating ............................................................... 7 3.5 result of exceeding a rating .............................................. 8 3.6 relationship between ratings and operating requirements...................................................................... 8 3.7 guidelines for ratings and operating requirements............ 8 3.8 definition: typical value..................................................... 9 3.9 typical value conditions .................................................... 10 4 ratings ...................................................................................... 10 4.1 thermal handling ratings ................................................... 10 4.2 moisture handling ratings .................................................. 11 4.3 esd handling ratings ......................................................... 11 4.4 voltage and current operating ratings ............................... 11 5 general ..................................................................................... 12 5.1 ac electrical characteristics .............................................. 12 5.2 nonswitching electrical specifications ............................... 12 5.2.1 voltage and current operating requirements ...... 12 5.2.2 lvd and por operating requirements ............... 14 5.2.3 voltage and current operating behaviors ............ 15 5.2.4 power mode transition operating behaviors ....... 17 5.2.5 power consumption operating behaviors............ 18 5.2.6 emc radiated emissions operating behaviors .... 22 5.2.7 designing with radiated emissions in mind ......... 23 5.2.8 capacitance attributes ........................................ 23 5.3 switching specifications..................................................... 23 5.3.1 device clock specifications ................................. 23 5.3.2 general switching specifications......................... 24 5.4 thermal specifications ....................................................... 26 5.4.1 thermal operating requirements......................... 26 5.4.2 thermal attributes ............................................... 26 5.5 power sequencing ............................................................. 27 6 peripheral operating requirements and behaviors .................... 27 6.1 core modules .................................................................... 27 6.1.1 debug trace timing specifications ....................... 27 6.1.2 jtag electricals.................................................. 28 6.2 system modules ................................................................ 31 6.3 clock modules ................................................................... 31 6.3.1 mcg specifications ............................................. 31 6.3.2 oscillator electrical specifications ....................... 34 6.3.3 32 khz oscillator electrical characteristics ........ 36 6.4 memories and memory interfaces ..................................... 37 6.4.1 flash (ftfe) electrical specifications ................. 37 6.4.2 ezport switching specifications ......................... 41 6.4.3 nfc specifications .............................................. 42 6.4.4 ddr controller specifications.............................. 45 6.4.5 flexbus switching specifications........................ 48 6.5 security and integrity modules .......................................... 50 6.5.1 dryice tamper electrical specifications ............. 50 6.6 analog ............................................................................... 51 6.6.1 adc electrical specifications .............................. 51 6.6.2 cmp and 6-bit dac electrical specifications ...... 59 6.6.3 12-bit dac electrical characteristics ................... 61 6.6.4 voltage reference electrical specifications.......... 64 6.7 timers................................................................................ 65 6.8 communication interfaces ................................................. 65 6.8.1 ethernet switching specifications ........................ 65 6.8.2 usb electrical specifications............................... 67 6.8.3 usb dcd electrical specifications ...................... 67 6.8.4 usb vreg electrical specifications ................... 68 6.8.5 ulpi timing specifications................................... 68 6.8.6 can switching specifications .............................. 69 6.8.7 dspi switching specifications (limited voltage range) ................................................................. 70 6.8.8 dspi switching specifications (full voltage range) ................................................................. 71 6.8.9 i2c switching specifications ................................ 73 6.8.10 uart switching specifications............................ 73 6.8.11 sdhc specifications ........................................... 73 k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 3 6.8.12 i2s/sai switching specifications ........................ 75 6.9 human-machine interfaces (hmi)...................................... 81 6.9.1 tsi electrical specifications ................................ 81 6.9.2 lcdc electrical specifications ............................ 82 7 dimensions ............................................................................... 85 7.1 obtaining package dimensions ......................................... 85 8 pinout ........................................................................................ 85 8.1 pins with active pull control after reset .............................. 85 8.2 k70 signal multiplexing and pin assignments .................. 85 8.3 k70 pinouts ....................................................................... 94 9 revision history ........................................................................ 95 k70 sub-family data sheet, rev. 4, 10/2012. 4 freescale semiconductor, inc. 1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: pk70 and mk70. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status m = fully qualified, general market flow p = prequalification k## kinetis family k70 a key attribute f = cortex-m4 w/ dsp and fpu m flash memory type n = program flash only x = program flash and flexmemory fff program flash memory size 512 = 512 kb 1m0 = 1 mb table continues on the next page... rdering parts 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 5 field description values t temperature range (c) v = ?40 to 105 c = ?40 to 85 pp package identifier mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) 12 = 120 mhz n packaging type r = tape and reel (blank) = trays 2.4 example this is an example part number: mk70fn1m0vmj12 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip ample his is an eample o an operating requirement hich you must meet or the accompanying operating behaviors to be guaranteed ymbol escription in a nit core supply voltage einition operating behavior n operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions erminology and guidelines ubamily ata heet ev reescale emiconductor nc 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements ample his is an eample o an attribute ymbol escription in a nit nput capacitance digital pins p einition ating rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating erminology and guidelines ubamily ata heet ev reescale emiconductor nc symbol description min. max. unit v dd 1.0 v core supply voltage ?0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 3.6 relationship between ratings and operating requirements ? ? never exceed any of the chip?s ratings. ? during normal operation, don?t exceed any of the chip?s operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed ample his is an eample o an operating behavior that includes a typical value ymbol escription in yp a nit igital o ea pulluppulldon current ample his is an eample o a chart that shos typical values or various voltage and temperature conditions erminology and guidelines ubamily ata heet ev reescale emiconductor nc 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c ?40 c v dd (v) i (?a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature ?55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings 0 sub-family data sheet, rev. , 10/2012. 10 freescale semiconductor, inc. 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . esd handling ratings symbol description min. max. nit notes hbm electrostatic discharge voltage, human body model -2000 2000 1 cdm electrostatic discharge voltage, charged-device model -500 500 2 i lat latch-up current at ambient temperature of 105c -100 100 ma 1. determined according to jedec standard jesd22-a11, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . oltage and current operating ratings symbol description min. max. nit dd digital supply voltage 1 0. . ddint core supply voltage 0. . ddddr ddr i/ supply voltage 0. . i dd digital supply current 00 ma i ddint core supply current 15 ma i ddddr ddr supply current 220 ma di digital input voltage (except reset, etal0/tal0, and etal1/tal1) 2 0. 5.5 dddr ddr input voltage 0. ddddr 0. ai analog , reset, etal0/tal0, and etal1/tal1 input voltage 0. dd 0. i d maximum current single pin limit (applies to all digital pins) 25 25 ma dda analog supply voltage dd 0. dd 0. sbdp sbdp input voltage 0. . sbdm sbdm input voltage 0. . regin sb regulator input 0. .0 table continues on the next page... ratings 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 11 symbol description min. max. unit v bat rtc battery supply voltage ?0.3 3.8 v 1. it applies for all port pins except tamper pins. 2. it covers digital pins except tamper pins and ddr pins. 3. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications general k70 sub-family data sheet, rev. 4, 10/2012. 12 freescale semiconductor, inc. 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage max(v dd_dd r ,2.0) 3.6 v v dd_int core supply voltage 1.71 v dd v v dd_ddr ddr voltage memory i/o buffers ddr1 ddr2/lpddr 2.3 1.7 2.7 1.9 v v v ref_ddr input reference voltage (ddr1/ddr2) 0.49 ? v dd_ddr 0.51 ? v dd_ddr v v dda analog supply voltage 1.71 3.6 v v dd ? v dda v dd -to-v dda differential voltage ?0.1 0.1 v v ss ? v ssa v ss -to-v ssa differential voltage ?0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage (digital pins except tamper pins and ddr pins) 2.7 v v dd 3.6 v 1.7 v v dd 2.7 v 0.7 ? v dd 0.75 ? v dd v v v il input low voltage (digital pins except tamper pins and ddr pins) 2.7 v v dd 3.6 v 1.7 v v dd 2.7 v 0.35 ? v dd 0.3 ? v dd v v v ih_ddr input high voltage (ddr pins) ddr1 ddr2 lpddr v ref_ddr + 0.15 v ref_ddr + 0.125 0.7 ? v dd_ddr v v v v il_ddr input low voltage (ddr pins) ddr1 ddr2 lpddr v ref_ddr ? 0.15 v ref_ddr ? 0.125 0.3 ? v dd_ddr v v v v hys input hysteresis (digital pins except tamper pins and ddr pins) 0.06 ? v dd v i icdio digital pin (except tamper pins) negative dc injection current single pin v in < v ss -0.3v -5 ma 1 table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 1 table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i icaio analog 2 , extal0/xtal0, and extal1/xtal1 pin dc injection current single pin v in < v ss -0.3v (negative current injection) v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins negative current injection positive current injection -25 +25 ma v ram v dd (v dd_int ) voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v dio_min (=v ss -0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i ic |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calculated as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. 5.2.2 lvd and por operating requirements table 2. lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. 1 freescale semiconductor, inc. table 2. lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 ?s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength 2.7 v v dd 3.6 v, i oh = -9ma 1.71 v v dd 2.7 v, i oh = -3ma v dd ? 0.5 v dd ? 0.5 v v output high voltage low drive strength 2.7 v v dd 3.6 v, i oh = -2ma 1.71 v v dd 2.7 v, i oh = -0.6ma v dd ? 0.5 v dd ? 0.5 v v i oht output high current total for all ports 100 ma i oht_io60 output high current total for fast digital ports 100 ma table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 15 table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes v oh_ddr output high voltage for ddr pins ddr1 (i oh = -16.2 ma) ddr2 half strength (i oh = -5.36 ma) ddr2 full strength (i oh = -13.4 ma) lpddr half strength (i oh = -0.1 ma) lpddr full strength (i oh = -0.1 ma) v dd_ddr - 0.36 v dd_ddr - 0.28 v dd_ddr - 0.28 0.9 x v dd_ddr 0.9 x v dd_ddr v v v v v i oht_ddr output high current total for ddr pins ddr1 ddr2 lpddr 100 56 39 ma ma ma v oh_tamper output high voltage high drive strength 2.7 v v bat 3.6 v, i oh = -10ma 1.71 v v bat 2.7 v, i oh = -3ma v bat ? 0.5 v bat ? 0.5 v v output high voltage low drive strength 2.7 v v bat 3.6 v, i oh = -2ma 1.71 v v bat 2.7 v, i oh = -0.6ma v bat ? 0.5 v bat ? 0.5 v v i oh_tamper output high current total for tamper pins 100 ma v ol output low voltage high drive strength 2.7 v v dd 3.6 v, i ol = 9ma 1.71 v v dd 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength 2.7 v v dd 3.6 v, i ol = 2ma 1.71 v v dd 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i olt_io60 output low current total for fast digital ports 100 ma v ol_ddr output low voltage for ddr pins ddr1 (i ol = 16.2 ma) ddr2 half strength (i ol = 5.36 ma) ddr2 full strength (i ol = 13.4 ma) lpddr half strength (i ol = 0.1 ma) lpddr full strength (i ol = 0.1 ma) 0.37 0.28 0.28 0.1 x v dd_ddr 0.1 x v dd_ddr v v v v v table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. 1 freescale semiconductor, inc. table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes i olt_ddr output low current total for ddr pins ddr1 ddr2 lpddr 100 56 39 ma ma ma v ol_tamper output low voltage high drive strength 2.7 v v bat 3.6 v, i ol = 10ma 1.71 v v bat 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength 2.7 v v bat 3.6 v, i ol = 2ma 1.71 v v bat 2.7 v, i ol = 0.6ma 0.5 0.5 v v i ol_tamper output low current total for tamper pins 100 ma i in input leakage current (per pin) for full temperature range 1 ?a 1 i in input leakage current (per pin) at 25c 0.025 ?a 1 i in_ddr input leakage current (per ddr pin) for full temperature range 1 ?a i in_ddr input leakage current (per ddr pin) at 25c 0.025 ?a i in_tamper input leakage current (per tamper pin) for full temperature range 1 ?a i in_tamper input leakage current (per tamper pin) at 25c 0.025 ?a i oz hi-z (off-state) leakage current (per pin) 1 ?a i oz_ddr hi-z (off-state) leakage current (per ddr pin) 1 ?a i oz_tamper hi-z (off-state) leakage current (per tamper pin) 1 ?a r pu internal pullup resistors (except tamper pins) 20 50 k? 2 r pd internal pulldown resistors (except tamper pins) 20 50 k? 3 r odt on-die termination (odt) resistance for ddr2 r tt1(eff) - 75 - 150 ? flexbus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 ?s 1 vlls1 table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. 1 freescale semiconductor, inc. table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_stop stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 1.3 3.0 7.5 3.8 27 42 ma ma ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.4 32 ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 2.2 38 ma 6 i dd_vlpw very-low-power wait mode current at 3.0 v 0.926 22 ma 7 i dd_vlps very-low-power stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 0.25 0.85 2.4 1.3 7.6 12.54 ma ma ma i dd_lls low leakage stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 0.25 0.85 2.4 1.3 7.6 12.54 ma ma ma i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 5.6 30.1 120.8 20 137 246 ?a ?a ?a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 3.2 11.8 51.2 14 40 60 ?a ?a ?a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 2.8 8.7 39.3 12 29 43 ?a ?a ?a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v @ ?40 to 25c @ 70c @ 105c 0.91 1.5 4.3 1.1 1.85 4.3 ?a ?a ?a 8 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus, 30 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. general k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 19 3. 120 mhz core and system clock, 60 mhz bus, 50 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 25 mhz core and system clock, 25 mhz bus clock, and 12.5 mhz flexbus and flash clock. mcg configured for fei mode. 5. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 0.5 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 6. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 0.5 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 7. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 0.5 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 8. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. mcg in pee mode is greater than 100 mhz frequencies. ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl general k70 sub-family data sheet, rev. 4, 10/2012. 20 freescale semiconductor, inc. figure 2. run mode supply current vs. core frequency general k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 21 figure 3. vlpr mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 256mapbga symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15?50 21 db?v 1 , 2 v re2 radiated emissions voltage, band 2 50?150 24 db?v v re3 radiated emissions voltage, band 3 150?500 29 db?v v re4 radiated emissions voltage, band 4 500?1000 28 db?v 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each freuency range. 2. dd . , t a 25 c, f sc 12 mhz (crystal), f ss 2 mhz, f bs 2mhz general 0 sub-family data sheet, rev. , 10/2012. 22 freescale semiconductor, inc. 5.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 5.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf c in_d_io60 input capacitance: fast digital pins 9 pf 5.3 switching specifications 5.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 120 mhz f sys_usbfs system and core clock when full speed usb in operation 20 mhz f sys_usbhs system and core clock when high speed usb in operation 60 mhz f enet system and core clock when ethernet in operation 10 mbps 100 mbps 5 50 mhz f bus bus clock 60 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz f ddr ddr clock 150 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 2 table 9. device clock specifications (continued) symbol description min. max. unit notes f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 0.5 mhz f lptmr lptmr clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, ieee 1588 timer, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 14 8 36 24 ns ns ns ns 4 port rise and fall time (low drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 14 8 36 24 ns ns ns ns 5 table continues on the next page... general 0 sub-family data sheet, rev. , 10/2012. 2 freescale semiconductor, inc. table 10. general switching specifications (continued) symbol description min. max. unit notes t io50 port rise and fall time (high drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 7 3 28 14 ns ns ns ns 6 t io50 port rise and fall time (low drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 18 9 48 24 ns ns ns ns 7 t io60 port rise and fall time (high drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 6 3 28 14 ns ns ns ns 6 t io60 port rise and fall time (low drive strength) slew disabled 1.71 v dd 2.7v 2.7 v dd 3.6v slew enabled 1.71 v dd 2.7v 2.7 v dd 3.6v 18 6 48 24 ns ns ns ns 7 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75pf load 5. 15pf load 6. 25pf load 7. 15pf load general k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 25 5.4 thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature ?40 125 c t a ambient temperature ?40 105 c 5.4.2 thermal attributes board type symbol description 256 mapbga unit notes single-layer (1s) r 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51- specification. . determined according to jedec standard jesd51-, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. . determined according to jedec standard jesd51-, integrated circuit thermal test method environmental conditionsjunction-to-board . board temperature is measured on the top surface of the board near the package. 5. determined according to method 1012.1 of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. . determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 5.5 power seuencing oltage supplies must be seuenced in the proper order to avoid damaging internal diodes. there is no limit on how long after one supply powers up before the next supply must power up. note that dd and ddint can use the same power source. the power-up seuence is: 1. dd 2. ddint . dda . ddddr the power-down seuence is the reverse: 1. ddddr 2. dda . ddint . dd peripheral operating reuirements and behaviors .1 core modules .1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. nit t cyc clock period freuency dependent mhz t wl low pulse width 2 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 2 table 12. debug trace operating behaviors (continued) symbol description min. max. unit t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 4. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 5. trace data specifications 6.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 20 10 ns ns ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. 2 freescale semiconductor, inc. table 13. jtag limited voltage range electricals (continued) symbol description min. max. unit j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.4 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.4 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 29 j2 j3 j3 j4 j4 tclk (input) figure 6. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 7. boundary scan (jtag) timing peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 30 freescale semiconductor, inc. j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 8. test access port timing j14 j13 tclk trst figure 9. trst timing 6.2 system modules there are no specifications necessary for the devices system modules. 6.3 clock modules peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 31 6.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. 2 freescale semiconductor, inc. table 15. mcg specifications (continued) symbol description min. typ. max. unit notes j cyc_fll fll period jitter f vco = 48 mhz f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll0,1 f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll0 operating current vco @ 180 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 22) 2.8 ma 7 i pll pll0 operating current vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 4.7 ma 7 i pll pll1 operating current vco @ 180 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 22) 2.3 ma 7 i pll pll1 operating current vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 3.6 ma 7 t pll_lock lock detector detection time 100 ? 10 -6 + 1075(1/ f pll_ref ) s 8 j cyc_pll pll period jitter (rms) f vco = 180 mhz f vco = 360 mhz 100 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) f vco = 180 mhz f vco = 360 mhz 600 300 ps ps 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( 9. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. accumulated jitter depends on vco frequency and vdiv. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 16. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 500 200 300 950 1.2 1.5 na ?a ?a ?a ma ma 1 i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 25 400 500 2.5 3 4 ?a ?a ?a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 16. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 17. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz 1 f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 60 mhz 2 , 3 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 5 table 17. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 1000 ms 4 , 5 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 500 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. frequencies less than 8 mhz are not in the pll range. 2. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 3. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 4. proper pc board layout procedures must be followed to achieve specifications. 5. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode bu default and cannot be moved into high power/gain mode. 6.3.3 32 khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32 khz oscillator dc electrical specifications table 18. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m? c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 36 freescale semiconductor, inc. 6.3.3.2 32khz oscillator frequency specifications table 19. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 6.4 memories and memory interfaces 6.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 ?s t hversscr erase flash sector high-voltage time 13 113 ms 1 t hversblk128k erase flash block high-voltage time for 128 kb 104 1808 ms 1 t hversblk256k erase flash block high-voltage time for 256 kb 208 3616 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk128k t rd1blk256k read 1s block execution time 128 kb data flash 256 kb program flash 0.5 1.0 ms ms table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t rd1sec4k read 1s section execution time (4 kb flash) 100 ?s 1 t pgmchk program check execution time 80 ?s 1 t rdrsrc read resource execution time 40 ?s 1 t pgm8 program phrase execution time 70 150 ?s t ersblk128k t ersblk256k erase flash block execution time 128 kb data flash 256 kb program flash 110 220 925 1850 ms ms 2 t ersscr erase flash sector execution time 15 115 ms 2 t pgmsec4k program section execution time (4kb flash) 20 ms t rd1all read 1s all blocks execution time 1.0 ms t rdonce read once execution time 30 ?s 1 t pgmonce program once execution time 70 ?s t ersall erase all blocks execution time 650 5600 ms 2 t vfykey verify backdoor access key execution time 30 ?s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time control code 0x01 control code 0x02 control code 0x04 control code 0x08 200 70 70 150 150 30 ?s ?s ?s ?s t pgmpart64k t pgmpart256k program partition for eeprom execution time 64 kb flexnvm 256 kb flexnvm 235 240 ms ms t setramff t setram64k t setram128k t setram256k set flexram function execution time: control code 0xff 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 205 1.6 2.7 4.8 2.5 3.8 6.2 ?s ms ms ms t eewr8bers byte-write to erased flexram location execution time 140 225 ?s 3 t eewr8b64k t eewr8b128k t eewr8b256k byte-write to flexram execution time: 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 400 450 525 1700 1800 2000 ?s ?s ?s t eewr16bers 16-bit write to erased flexram location execution time 140 225 ?s table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr16b64k t eewr16b128k t eewr16b256k 16-bit write to flexram execution time: 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 400 450 525 1700 1800 2000 ?s ?s ?s t eewr32bers 32-bit write to erased flexram location execution time 180 275 ?s t eewr32b64k t eewr32b128k t eewr32b256k 32-bit write to flexram execution time: 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 475 525 600 1850 2000 2200 ?s ?s ?s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash high voltage current behaviors table 22. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 23. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmcycee cycling endurance for eeprom backup 20 k 50 k cycles 2 n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree2k n nvmwree4k write endurance eeprom backup to flexram ratio = 16 eeprom backup to flexram ratio = 128 eeprom backup to flexram ratio = 512 eeprom backup to flexram ratio = 2,048 eeprom backup to flexram ratio = 4,096 70 k 630 k 2.5 m 10 m 20 m 175 k 1.6 m 6.4 m 25 m 50 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfe to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = ? write_efficiency ? n eeprom ? 2 ? eeesplit ? eeesize eeesplit ? eeesize nvmcycee where ? writes_subsystem ? minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 40 freescale semiconductor, inc. ? eeprom ? allocated flexnvm for each eeprom subsystem based on depart; entered with program partition command ? eeesplit ? flexram split factor for subsystem; entered with the program partition command ? eeesize ? allocated flexram based on depart; entered with program partition command ? write_efficiency ? ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycee ? eeprom-backup cycling endurance figure 10. eeprom backup writes to flexram 6.4.2 ezport switching specifications table 24. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 1 table 24. ezport switching specifications (continued) num description min. max. unit ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 11. ezport timing diagram 6.4.3 nfc specifications the nand flash controller (nfc) implements the interface to standard nand flash memory devices. this section describes the timing parameters of the nfc. in the following table: ? t h is the flash clock high time and ? t l is flash clock low time, peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 42 freescale semiconductor, inc. which are defined as: input clock t scaler = nfc t = h t l t + the scaler value is derived from the fractional divider specified in the sims clkdiv4 register: scaler = sim_clkdiv4[nfcfrac] + 1 sim_clkdiv4[nfcdiv] + 1 in case the reciprocal of scaler is an integer, the duty cycle of nfc clock is 50%, means t h = t l . in case the reciprocal of scaler is not an integer: (1 + scaler / 2) x = l t nfc t 2 (1 ? scaler / 2) x = h t nfc t 2 for example, if scaler is 0.2, then t h = t l = t nfc /2. t nfc t h t l however, if scaler is 0.667, then t l = 2/3 x t nfc and t h = 1/3 x t nfc . t nfc t h t l note the reciprocal of scaler must be a multiple of 0.5. for example, 1, 1.5, 2, 2.5, etc. table 25. nfc specifications num description min. max. unit t cls nfc_cle setup time 2t h + t l ? 1 ns t clh nfc_cle hold time t h + t l ? 1 ns t cs nfc_cen setup time 2t h + t l ? 1 ns t ch nfc_cen hold time t h + t l ns t wp nfc_wp pulse width t l ? 1 ns t als nfc_ale setup time 2t h + t l ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 25. nfc specifications (continued) num description min. max. unit t alh nfc_ale hold time t h + t l ns t ds data setup time t l ? 1 ns t dh data hold time t h ? 1 ns t wc write cycle time t h + t l ? 1 ns t wh nfc_we hold time t h ? 1 ns t rr ready to nfc_re low 4t h + 3t l + 90 ns t rp nfc_re pulse width t l + 1 ns t rc read cycle time t l + t h ? 1 ns t reh nfc_re high hold time t h ? 1 ns t is data input setup time 11 ns tcs tchtwp tds tdh tcls tclh nfc_cle nfc_cen nfc_we nfc_ion figure 12. command latch cycle timing tcs tchtwp tds tdh tals talh address nfc_ale nfc_cen nfc_we nfc_ion figure 13. address latch cycle timing peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 44 freescale semiconductor, inc. tcs tch twp tds tdh data data data twc twh nfc_cen nfc_we nfc_ion figure 14. write data latch cycle timing tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 15. read data latch cycle timing in non-fast mode tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 16. read data latch cycle timing in fast mode 6.4.4 ddr controller specifications the following timing numbers must be followed to properly latch or drive data onto the ddr memory bus. all timing numbers are relative to the dqs byte lanes. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 45 table 26. ddr controller ac timing specifications symbol description min. max. unit notes frequency of operation ddr1 ddr2 lpddr 83.3 125 1 50 150 150 150 mhz mhz mhz 2 t ddrck clock period ddr1 ddr2 lpddr 6.6 6.6 6.6 12 8 20 ns ns ns v ox-ac ddrck ac differential cross point voltage ddr1 ddr2 lpddr 0.5 x v dd_ddr ? 0.2 v 0.5 x v dd_ddr ? 0.125 v 0.4 x v dd_ddr 0.5 x v dd_ddr + 0.2 v 0.5 x v dd_ddr + 0.125 v 0.4 x v dd_ddr v v v t ddrckh pulse width high 0.45 0.55 t ddrck 3 t ddrckl pulse width low 0.45 0.55 t ddrck 3 t cmv address, ddr_cke, ddr_cas, ddr_ras, ddr_we, ddr_csn output valid 0.5 x t ddrck ? 1 ns 4 t cmh address, ddr_cke, ddr_cas, ddr_ras, ddr_we, ddr_csn output hold 0.5 x t ddrck ? 1 ns t dqss dqs rising edge to ck rising edge 0.2 x t ddrck 0.2 x t ddrck ns t qs data and data mask output setup (dq 1 2 3 4 5 6 7 8 9 10 cmd cmd colrow wd1 wd2 wd3 wd4 tddrck tddrckh tddrckl tcmv tcmh tqh tqs tdqss ddr_clk ddr__clk ddr_csn, ddr_we ddr_cas, ddr_ras ddr_an ddr_dqsn ddr_dmn ddr_dqn figure 17. ddr write timing 1 2 3 4 5 6 7 8 9 10 11 12 cmd row col rd1 rd2 rd3rd4 rd1 rd2rd3rd4 cmd dqs read preamble dqs read preamble tddrck tddrchh tddrckl cl=3.0 tcmv cl=2.5 tcmh ddr_clk ddr__clk ddr_csn, ddr_we ddr_cas, ddr_ras ddr_an ddr_dqs (cl=2.5) ddr_dqn (cl=2.5) ddr_dqs (cl=3.0) ddr_dqn (cl=3.0) rd3 rd4 rd1 rd2 rd3 rd4 figure 18. ddr read timing peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 47 figure 19. ddr read timing, dq vs. dqs 6.4.5 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 27. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fbcs n , fbe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. 2. specification is valid for all fbad1:0 and fbta. table 2. flexbus full voltage range switching specifications num description min. max. nit notes perating voltage 1.1 . freuency of operation fbcl mhz fb1 clock period 1/fbcl ns fb2 address, data, and control output valid 1.5 ns 1 fb address, data, and control output hold 0 ns 1 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 28. flexbus full voltage range switching specifications (continued) num description min. max. unit notes fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fbcs n , fbe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. 2. specification is valid for all fbad1:0 and fbta. address address data tsi aa1 aa0 aa1 aa0 fb1 fb fb5 fb fb fb5 fb2 fbcl fba fbd fbrw fbts fbale fbcsn fben fbben fbta fbtsi1:0 figure 20. flexbus read timing diagram peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 21. flexbus write timing diagram 6.5 security and integrity modules 6.5.1 dryice tamper electrical specifications information about security-related modules is not included in this document and is available only after a nondisclosure agreement (nda) has been signed. to request an nda, please contact your local freescale sales representative. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 50 freescale semiconductor, inc. 6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 29 and table 30 are achievable on the differential pins adcx_dp0, adcx_dm0. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 31 and table 32 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 29. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 51 table 29. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance must be kept as low as possible to achieve the best results. the results in this data sheet were derived from a system which has < 8 ? analog source resistance. the r as /c as time constant should be kept to < 1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit must be set and the adlpc bit must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin 6.6.1.2 16-bit adc electrical characteristics table 30. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source adlpc = 1, adhsc = 0 adlpc = 1, adhsc = 1 adlpc = 0, adhsc = 0 adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error 12-bit modes <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity 12-bit modes <12-bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity 12-bit modes <12-bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error 12-bit modes <12-bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error 16-bit modes 13-bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode avg = 32 avg = 4 16-bit single-ended mode avg = 32 avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 ? enob + 1.76 db thd total harmonic distortion 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 ?94 -85 db db 7 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 5 table 30. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes sfdr spurious free dynamic range 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 82 78 95 90 db db 7 e il input leakage error i in ? r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.715 mv/c v temp25 temp sensor voltage 25 c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit must be set, the hsc bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 54 freescale semiconductor, inc. figure 23. typical enob vs. adc_clk for 16-bit differential mode figure 24. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 55 6.6.1.3 16-bit adc with pga operating conditions table 31. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k? in+ to in- 4 r as analog source resistance 100 ? 5 t s adc sampling time 1.25 s 6 c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 56 freescale semiconductor, inc. 6.6.1.4 16-bit adc with pga characteristics table 32. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 ?a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 ?a gain =64, v refpga =1.2v, v cm =0.1v 0.57 ?a g gain 4 pgag=0 pgag=1 pgag=2 pgag=3 pgag=4 pgag=5 pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 5 table 32. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes e il input leakage error all modes i in ? r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga ? 0.583 v 6 snr signal-to-noise ratio gain=1 gain=64 80 52 90 66 db db 16-bit differential mode, average=32 thd total harmonic distortion gain=1 gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz sfdr spurious free dynamic range gain=1 gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits gain=1, average=4 gain=1, average=8 gain=64, average=4 gain=64, average=8 gain=1, average=32 gain=2, average=32 gain=4, average=32 gain=8, average=32 gain=16, average=32 gain=32, average=32 gain=64, average=32 11.6 8.0 7.2 6.3 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 13.6 9.6 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100hz sinad signal-to-noise plus distortion ratio see enob 6.02 ? enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 58 freescale semiconductor, inc. 6.6.2 cmp and 6-bit dac electrical specifications table 33. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 ?a i ddls supply current, low-speed mode (en=1, pmode=0) 20 ?a v ain analog input voltage v ss ? 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd ? 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 ?s i dac6b 6-bit dac current adder (enabled) 7 ?a inl 6-bit dac integral non-linearity ?0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity ?0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 59 0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 25. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 60 freescale semiconductor, inc. 0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 26. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 34. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature operating temperature range of the device c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 61 6.6.3.2 12-bit dac operating behaviors table 35. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 ?a i dda_dach p supply current high-speed mode 700 ?a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 ?s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 ?s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 ?s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr 100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda ? 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 ?v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k? 250 ? sr slew rate -80h figure 27. typical inl error vs. digital code peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 63 figure 28. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 36. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 64 freescale semiconductor, inc. table 37. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v v out voltage reference output factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.193 1.197 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only current 80 a 1 i hp high-power buffer current 1 ma 1 6.8.1 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 40. mii signal switching specifications symbol description min. max. unit rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns mii7mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 29. mii transmit signal timing diagram peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 66 freescale semiconductor, inc. mii2 mii1 mii4mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 30. mii receive signal timing diagram 6.8.1.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 41. rmii signal switching specifications num description min. max. unit extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15 ns 6.8.2 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 67 6.8.3 usb dcd electrical specifications table 42. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 ?a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 ?a i dm_sink usb_dm sink current 50 100 150 ?a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k? v dat_ref data detect voltage 0.25 0.325 0.4 v 6.8.4 usb vreg electrical specifications table 43. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 186 ?a i ddstby quiescent current standby mode, load current equal zero 1.1 10 ?a i ddoff quiescent current shutdown mode vregin = 5.0 v and temperature=25c across operating voltage and temperature 650 4 na ?a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v run mode standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 ?f esr external output capacitor equivalent series resistance 1 100 m? i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 68 freescale semiconductor, inc. 6.8.5 ulpi timing specifications the ulpi interface is fully compliant with the industry standard utmi+ low pin interface. control and data timing requirements for the ulpi pins are given in the following table. these timings apply to synchronous mode only. all timings are measured with respect to the clock as seen at the usb_clkin pin. table 44. ulpi timing specifications num description min. typ. max. unit usb_clkin operating frequency 60 mhz usb_clkin duty cycle 50 % u1 usb_clkin clock period 16.67 ns u2 input setup (control and data) 5 ns u3 input hold (control and data) 1 ns u4 output valid (control and data) 9.5 ns u5 output hold (control and data) 1 ns u1 u2 u3 u4 u5 usb_clkin ulpi_dir/ulpi_nxt (control input) ulpi_datan (input) ulpi_stp (control output) ulpi_datan (output) figure 31. ulpi timing diagram peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 69 6.8.6 can switching specifications see general switching specifications . 6.8.7 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 45. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) 2 ns 1 ds dspisc to dspipcs n invalid delay (t bs x 2) 2 ns 2 ds5 dspisc to dspist valid .5 ns ds dspisc to dspist invalid 2 ns ds dspisin to dspisc input setup 15 ns ds dspisc to dspisin input hold 0 ns 1. the delay is programmable in spixctarnpssc and spixctarncssc. 2. the delay is programmable in spixctarnpasc and spixctarnasc. ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure 2. dspi classic spi timing master mode peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. 0 freescale semiconductor, inc. table 46. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 33. dspi classic spi timing slave mode 6.8.8 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 47. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. 1 table 47. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) ns 2 ds dspisc to dspipcs n invalid delay (t bs x 2) ns ds5 dspisc to dspist valid 10 ns ds dspisc to dspist invalid -.5 ns ds dspisin to dspisc input setup 20.5 ns ds dspisc to dspisin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum freuency of operation is reduced. 2. the delay is programmable in spixctarnpssc and spixctarncssc. . the delay is programmable in spixctarnpasc and spixctarnasc. ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure . dspi classic spi timing master mode table . slave mode dspi timing (full voltage range) num description min. max. nit perating voltage 1.1 . freuency of operation .5 mhz ds dspisc input cycle time x t bs ns ds10 dspisc input high/low time (t sc /2) - (t sc/2) ns ds11 dspisc to dspist valid 20 ns ds12 dspisc to dspist invalid 0 ns ds1 dspisin to dspisc input setup 2 ns ds1 dspisc to dspisin input hold ns ds15 dspiss active to dspist driven 1 ns ds1 dspiss inactive to dspist not driven 1 ns peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. 2 freescale semiconductor, inc. first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 35. dspi classic spi timing slave mode 6.8.9 i 2 c switching specifications see general switching specifications . 6.8.10 uart switching specifications see general switching specifications . 6.8.11 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 49. sdhc switching specifications over a limited operating voltage range num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet, rev. , 10/2012. freescale semiconductor, inc. table 49. sdhc switching specifications over a limited operating voltage range (continued) num symbol description min. max. unit sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns table 50. sdhc switching specifications over the full operating voltage range num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 1.3 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 36. sdhc timing peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 74 freescale semiconductor, inc. 6.8.12 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.12.1 normal run, wait and stop mode performance over a limited operating voltage range this section provides the operating performance over a limited operating voltage for the device in normal run, wait and stop modes. table 51. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 75 s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 37. i2s/sai timing master modes table 52. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid multiple sai synchronous mode all other modes 21 15 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 76 freescale semiconductor, inc. s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 38. i2s/sai timing slave modes 6.8.12.2 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 53. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 20.5 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 77 s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 39. i2s/sai timing master modes table 54. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid multiple sai synchronous mode all other modes 24 20.6 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 78 freescale semiconductor, inc. s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 40. i2s/sai timing slave modes 6.8.12.3 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 55. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid -1.6 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 79 s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 41. i2s/sai timing master modes table 56. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 3 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 63 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 80 freescale semiconductor, inc. s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 42. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 57. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 15 mhz 2 , 3 f elemax electrode oscillator frequency 1 1.8 mhz 2 , 4 c ref internal reference capacitor 1 pf v delta oscillator delta voltage 600 mv 2 , 5 i ref reference oscillator current source base current 2 32 2 32 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. refchrg = 2, extchrg=0. 4. refchrg = 0, extchrg = 10. 5. v dd = 3.0 v. 6. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 7. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 8. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 10. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 11. sensitivity defines the minimum capacitance change when a single count from the tsi module changes. sensitivity depends on the configuration used. the documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (c ref * i ext )/( i ref * ps * nscn) the typical value is calculated with the following configuration: i ext = 6 = 16 = 2 = 32 glcd_d[17:0] glcd_lsclk t1 t3 t2 figure 43. glcd_lsclk to glcd_d[17:0] timing glcd_vsync glcd_hsync glcd_oe glcd_d[17:0] t2 t1 non-display region t4 t3 display region line y line y line 1 (1,1) t7 xmax t6 t5 glcd_hsync glcd_lsclk glcd_oe glcd_d[15:0] (1,2) (1,x) figure 44. 4/8/12/16/18 bit/pixel tft color mode panel timing table 59. 4/8/12/16/18 bit/pixel tft color mode panel timing num description min. max. unit t1 end of glcd_oe to beginning of glcd_vsync t5 + t6 + t7 ? 1 (vwait1 ? t2) + t5 + t6 + t7 ? 1 ts t2 glcd_hsync period xmax + t5 + t6 + t7 ts t3 glcd_vsync pulse width t2 vwidth ? t2 ts t4 end of glcd_vsync to beginning of glcd_oe 1 (vwait2 ? t2) + 1 ts t5 glcd_hsync pulse width 1 hwidth + 1 ts t6 end of glcd_hsync to beginning to glcd_oe 3 hwait2 + 3 ts t7 end of glcd_oe to beginning of glcd_hsync 1 hwait1 + 1 ts peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 83 note ? ts is the glcd_lsclk period. glcd_vsync, glcd_hsync, and glcd_oe can be programmed as active high or active low. in the preceding figure, all 3 signals are active low. glcd_lsclk can be programmed to be deactivated during the glcd_vsync pulse or the glcd_oe deasserted period. in the preceding figure, glcd_lsclk is always active. ? xmax is defined in number of pixels in one line. glcd_lsclk glcd_d[15:0] glcd_hsync t2 t1 t2 t3 xmax t4 ts glcd_vsync t1 figure 45. non-tft mode panel timing table 60. non-tft mode panel timing num description min. max. unit t1 glcd_hsync to glcd_vsync delay 2 hwait2 + 2 tpix t2 glcd_hsync pulse width 1 hwidth + 1 tpix t3 glcd_vsync to glcd_lsclk 0 t3 ts t4 glcd_lsclk to glcd_hsync 1 hwait1 + 1 tpix note ts is the glcd_lsclk period while tpix is the pixel clock period. glcd_vsync, glcd_hsync, and glcd_lsclk can be programmed as active high or active low. in the preceding figure, all these 3 signals are active high. when it is in cstn mode or monochrome mode with bus width = 1, t3 = tpix = ts. when it is in monochrome mode with bus width = 2, 4 and 8, t3 = 1, 2 and 4 tpix respectively. peripheral operating requirements and behaviors k70 sub-family data sheet, rev. 4, 10/2012. 84 freescale semiconductor, inc. 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number: if you want the drawing for this package then use this document number 256-pin mapbga 98asa00346d 8 pinout 8.1 pins with active pull control after reset the following pins are actively pulled up or down after reset: table 61. pins with active pull control after reset pin active pull direction after reset pta0 pulldown pta1 pullup pta3 pullup pta4 pullup reset_b pullup 8.2 k70 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport e2 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 glcd_d0 i2c1_sda rtc_clkout dimensions k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 85 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport f2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 glcd_d1 i2c1_scl spi1_sin f3 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_b sdhc0_dclk glcd_d2 g2 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_b sdhc0_cmd glcd_d3 spi1_sout g7 vdd vdd vdd h7 vddint vddint vddint h8 vss vss vss f1 ptf17 disabled ptf17 spi2_sck ftm0_ch4 uart0_rx glcd_d13 g1 ptf18 disabled ptf18 spi2_sout ftm1_ch0 uart0_tx glcd_d14 g3 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 glcd_d4 g4 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 glcd_d5 ftm3_ch0 h2 pte6 disabled pte6 spi1_pcs3 uart3_cts_b i2s0_mclk glcd_d6 ftm3_ch1 usb_sof_ out h1 ptf19 disabled ptf19 spi2_sin ftm1_ch1 uart5_rx glcd_d15 h5 ptf20 disabled ptf20 spi2_pcs1 ftm2_ch0 uart5_tx glcd_d16 h3 pte7 disabled pte7 uart3_rts_b i2s0_rxd0 glcd_d7 ftm3_ch2 h4 pte8 adc2_se16 adc2_se16 pte8 i2s0_rxd1 uart5_tx i2s0_rx_fs glcd_d8 ftm3_ch3 j1 pte9 adc2_se17 adc2_se17 pte9 i2s0_txd1 uart5_rx i2s0_rx_bclk glcd_d9 ftm3_ch4 j2 pte10 disabled pte10 uart5_cts_b i2s0_txd0 glcd_d10 ftm3_ch5 k1 pte11 adc3_se16 adc3_se16 pte11 uart5_rts_b i2s0_tx_fs glcd_d11 ftm3_ch6 k3 pte12 adc3_se17 adc3_se17 pte12 i2s0_tx_bclk glcd_d12 ftm3_ch7 g8 vdd vdd vdd h9 vss vss vss j3 pte16 adc0_se4a adc0_se4a pte16 spi0_pcs0 uart2_tx ftm_clkin0 ftm0_flt3 k2 pte17 adc0_se5a adc0_se5a pte17 spi0_sck uart2_rx ftm_clkin1 lptmr0_alt3 l4 pte18 adc0_se6a adc0_se6a pte18 spi0_sout uart2_cts_b i2c0_sda m3 pte19 adc0_se7a adc0_se7a pte19 spi0_sin uart2_rts_b i2c0_scl cmp3_out l2 vss vss vss m1 usb0_dp usb0_dp usb0_dp m2 usb0_dm usb0_dm usb0_dm l1 vout33 vout33 vout33 l3 vregin vregin vregin n1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 n2 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pinout k70 sub-family data sheet, rev. 4, 10/2012. 86 freescale semiconductor, inc. 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport p1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 p2 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 r1 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 r2 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 t1 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 t2 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 n5 vdda vdda vdda p4 vrefh vrefh vrefh m4 vrefl vrefl vrefl n4 vssa vssa vssa p3 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 n3 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 t3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 r3 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 r4 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 m5 tamper0/ rtc_ wakeup_b tamper0/ rtc_ wakeup_b tamper0/ rtc_ wakeup_b l5 tamper1 tamper1 tamper1 l6 tamper2 tamper2 tamper2 r5 tamper3 tamper3 tamper3 p6 tamper4 tamper4 tamper4 pinout k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 87 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport r6 tamper5 tamper5 tamper5 t6 xtal32 xtal32 xtal32 t5 extal32 extal32 extal32 p5 vbat vbat vbat n6 tamper6 tamper6 tamper6 m6 tamper7 tamper7 tamper7 g9 vdd vdd vdd h10 vddint vddint vddint j8 vss vss vss p7 pte24 adc0_se17/ extal1 adc0_se17/ extal1 pte24 can1_tx uart4_tx i2s1_tx_fs glcd_d13 ewm_out_b i2s1_rxd1 r7 pte25 adc0_se18/ xtal1 adc0_se18/ xtal1 pte25 can1_rx uart4_rx i2s1_tx_bclk glcd_d14 ewm_in i2s1_txd1 m7 pte26 adc3_se5b adc3_se5b pte26 enet_1588_ clkin uart4_cts_b i2s1_txd0 glcd_d15 rtc_clkout usb_clkin k7 pte27 adc3_se4b adc3_se4b pte27 uart4_rts_b i2s1_mclk glcd_d16 l7 pte28 adc3_se7a adc3_se7a pte28 glcd_d17 t7 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b/ uart0_col_b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk n8 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di t8 pta2 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do p8 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_b ftm0_ch0 jtag_tms/ swd_dio r8 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b t12 pta5 disabled pta5 usb_clkin ftm0_ch2 rmii0_rxer/ mii0_rxer cmp2_out i2s0_tx_bclk jtag_trst_b g10 vdd vdd vdd j9 vss vss vss p9 ptf21 adc3_se6b adc3_se6b ptf21 ftm2_ch1 uart5_rts_b glcd_d17 n9 ptf22 adc3_se7b adc3_se7b ptf22 i2c0_scl ftm1_ch0 uart5_cts_b glcd_d18 r12 pta6 adc3_se6a adc3_se6a pta6 ulpi_clk ftm0_ch3 i2s1_rxd0 clkout trace_ clkout p12 pta7 adc0_se10 adc0_se10 pta7 ulpi_dir ftm0_ch4 i2s1_rx_bclk trace_d3 n12 pta8 adc0_se11 adc0_se11 pta8 ulpi_nxt ftm1_ch0 i2s1_rx_fs ftm1_qd_ pha trace_d2 t13 pta9 adc3_se5a adc3_se5a pta9 ulpi_stp ftm1_ch1 mii0_rxd3 ftm1_qd_ phb trace_d1 p13 pta10 adc3_se4a adc3_se4a pta10 ulpi_data0 ftm2_ch0 mii0_rxd2 ftm2_qd_ pha trace_d0 pinout k70 sub-family data sheet, rev. 4, 10/2012. 88 freescale semiconductor, inc. 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport r13 pta11 adc3_se15 adc3_se15 pta11 ulpi_data1 ftm2_ch1 mii0_rxclk ftm2_qd_ phb m10 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_rxd1/ mii0_rxd1 i2s0_txd0 ftm1_qd_ pha n10 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 rmii0_rxd0/ mii0_rxd0 i2s0_tx_fs ftm1_qd_ phb r11 pta14 cmp3_in0 cmp3_in0 pta14 spi0_pcs0 uart0_tx rmii0_crs_ dv/ mii0_rxdv i2s0_rx_bclk i2s0_txd1 p11 pta15 cmp3_in1 cmp3_in1 pta15 spi0_sck uart0_rx rmii0_txen/ mii0_txen i2s0_rxd0 t14 vss vss vss n11 pta16 cmp3_in2 cmp3_in2 pta16 spi0_sout uart0_cts_ b/ uart0_col_b rmii0_txd0/ mii0_txd0 i2s0_rx_fs i2s0_rxd1 t11 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_b rmii0_txd1/ mii0_txd1 i2s0_mclk p10 ptf23 adc3_se10 adc3_se10 ptf23 i2c0_sda ftm1_ch1 trace_ clkout glcd_d19 r10 ptf24 adc3_se11 adc3_se11 ptf24 can1_rx ftm1_qd_ pha trace_d3 glcd_d20 r9 ptf25 adc3_se12 adc3_se12 ptf25 can1_tx ftm1_qd_ phb trace_d2 glcd_d21 t9 ptf26 adc3_se13 adc3_se13 ptf26 ftm2_qd_ pha trace_d1 glcd_d22 t10 ptf27 adc3_se14 adc3_se14 ptf27 ftm2_qd_ phb trace_d0 glcd_d23 j7 vdd vdd vdd k8 vss vss vss t15 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 t16 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_alt1 r16 reset_b reset_b reset_b n13 pta24 cmp3_in4 cmp3_in4 pta24 ulpi_data2 mii0_txd2 fb_a29 r14 pta25 cmp3_in5 cmp3_in5 pta25 ulpi_data3 mii0_txclk fb_a28 m13 pta26 adc2_se15 adc2_se15 pta26 ulpi_data4 mii0_txd3 fb_a27 r15 pta27 adc2_se14 adc2_se14 pta27 ulpi_data5 mii0_crs fb_a26 p14 pta28 adc2_se13 adc2_se13 pta28 ulpi_data6 mii0_txer fb_a25 n14 pta29 adc2_se12 adc2_se12 pta29 ulpi_data7 mii0_col fb_a24 p16 ptf0 adc2_se11 adc2_se11 ptf0 can0_tx ftm3_ch0 i2s1_rxd1 glcd_pclk l13 ptf1 adc2_se10 adc2_se10 ptf1 can0_rx ftm3_ch1 i2s1_rx_bclk glcd_de m12 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 rmii0_mdio/ mii0_mdio ftm1_qd_ pha pinout k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 89 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport m11 ptb1 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc/ mii0_mdc ftm1_qd_ phb p15 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_b enet0_1588_ tmr0 ftm0_flt3 m14 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_b enet0_1588_ tmr1 ftm0_flt0 n15 ptb4 adc1_se10 adc1_se10 ptb4 glcd_ contrast enet0_1588_ tmr2 ftm1_flt0 m15 ptb5 adc1_se11 adc1_se11 ptb5 enet0_1588_ tmr3 ftm2_flt0 l14 ptb6 adc1_se12 adc1_se12 ptb6 fb_ad23 l15 ptb7 adc1_se13 adc1_se13 ptb7 fb_ad22 k14 ptb8 disabled ptb8 uart3_rts_b fb_ad21 k15 ptb9 disabled ptb9 spi1_pcs1 uart3_cts_b fb_ad20 j13 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx i2s1_tx_bclk fb_ad19 ftm0_flt1 j14 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx i2s1_tx_fs fb_ad18 ftm0_flt2 k9 vss vss vss j10 vdd vdd vdd n16 ptf2 adc2_se6a adc2_se6a ptf2 i2c1_scl ftm3_ch2 i2s1_rx_fs glcd_hfs m16 ptf3 adc2_se7a adc2_se7a ptf3 i2c1_sda ftm3_ch3 i2s1_rxd0 glcd_vfs l16 ptf4 adc2_se4b adc2_se4b ptf4 ftm3_ch4 i2s1_txd0 glcd_d0 j15 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx i2s1_txd0 fb_ad17 ewm_in h13 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx i2s1_txd1 fb_ad16 ewm_out_b h14 ptb18 tsi0_ch11 tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_bclk fb_ad15 ftm2_qd_ pha k16 ptf5 adc2_se5b adc2_se5b ptf5 ftm3_ch5 i2s1_tx_fs glcd_d1 j16 ptf6 adc2_se6b adc2_se6b ptf6 ftm3_ch6 i2s1_tx_bclk glcd_d2 h15 ptb19 tsi0_ch12 tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb g13 ptb20 adc2_se4a adc2_se4a ptb20 spi2_pcs0 fb_ad31/ nfc_data15 cmp0_out g14 ptb21 adc2_se5a adc2_se5a ptb21 spi2_sck fb_ad30/ nfc_data14 cmp1_out g15 ptb22 disabled ptb22 spi2_sout fb_ad29/ nfc_data13 cmp2_out h16 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28/ nfc_data12 cmp3_out g16 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg fb_ad14/ nfc_data11 i2s0_txd1 f13 ptc1/ llwu_p6 adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_b ftm0_ch0 fb_ad13/ nfc_data10 i2s0_txd0 pinout k70 sub-family data sheet, rev. 4, 10/2012. 90 freescale semiconductor, inc. 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport f14 ptc2 adc0_se4b/ cmp1_in0/ tsi0_ch15 adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_b ftm0_ch1 fb_ad12/ nfc_data9 i2s0_tx_fs e13 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_bclk f15 ptf7 adc2_se7b adc2_se7b ptf7 ftm3_ch7 uart3_rx i2s1_txd1 glcd_d3 l9 vss vss vss k10 vdd vdd vdd f16 ptf8 disabled ptf8 ftm3_flt0 uart3_tx i2s1_mclk glcd_d4 e14 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11/ nfc_data8 cmp1_out i2s1_tx_bclk e15 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_alt2 i2s0_rxd0 fb_ad10/ nfc_data7 cmp0_out i2s1_tx_fs f12 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_bclk fb_ad9/ nfc_data6 i2s0_mclk g12 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_sof_ out i2s0_rx_fs fb_ad8/ nfc_data5 h12 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 ftm3_ch4 i2s0_mclk fb_ad7/ nfc_data4 f11 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_bclk fb_ad6/ nfc_data3 ftm2_flt0 g11 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl ftm3_ch6 i2s0_rx_fs fb_ad5/ nfc_data2 i2s1_mclk h11 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b/ nfc_we j12 ptc12 disabled ptc12 uart4_rts_b fb_ad27 ftm3_flt0 k13 ptc13 disabled ptc13 uart4_cts_b fb_ad26 j11 ptc14 disabled ptc14 uart4_rx fb_ad25 k12 ptf9 cmp2_in4 cmp2_in4 ptf9 uart3_rts_b glcd_d5 l12 ptf10 cmp2_in5 cmp2_in5 ptf10 uart3_cts_b glcd_d6 f10 ptc15 disabled ptc15 uart4_tx fb_ad24 n7 vss vss vss l10 vdd vdd vdd k11 ptf11 disabled ptf11 uart2_rts_b glcd_d7 l11 ptf12 disabled ptf12 uart2_cts_b glcd_d8 f9 ptc16 disabled ptc16 can1_rx uart3_rx enet0_1588_ tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_16_b nfc_rb e9 ptc17 disabled ptc17 can1_tx uart3_tx enet0_1588_ tmr1 fb_cs4_b/ fb_tsiz0/ fb_be31_24_b nfc_ce0_b m9 ptc18 disabled ptc18 uart3_rts_b enet0_1588_ tmr2 fb_tbst_b/ fb_cs2_b/ fb_be15_8_b nfc_ce1_b m8 ptc19 disabled ptc19 uart3_cts_b enet0_1588_ tmr3 fb_cs3_b/ fb_be7_0_b fb_ta_b pinout k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 91 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport l8 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b i2s1_rxd1 f8 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_b ftm3_ch1 fb_cs0_b i2s1_rxd0 k6 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm3_ch2 fb_ad4 i2s1_rx_fs j6 ptd3 disabled ptd3 spi0_sin uart2_tx ftm3_ch3 fb_ad3 i2s1_rx_bclk k5 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rts_b ftm0_ch4 fb_ad2/ nfc_data1 ewm_in j5 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_b ftm0_ch5 fb_ad1/ nfc_data0 ewm_out_b k4 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 h6 ptf13 disabled ptf13 uart2_rx glcd_d9 g6 ptf14 disabled ptf14 uart2_tx glcd_d10 t4 vss vss vss e7 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 j4 ptd8 disabled ptd8 i2c0_scl uart5_rx fb_a16/ nfc_cle f7 ptd9 disabled ptd9 i2c0_sda uart5_tx fb_a17/ nfc_ale e6 ptd10 disabled ptd10 uart5_rts_b fb_a18/ nfc_re g5 ptd11 disabled ptd11 spi2_pcs0 uart5_cts_b sdhc0_clkin fb_a19 glcd_ contrast f5 ptd12 disabled ptd12 spi2_sck ftm3_flt0 sdhc0_d4 fb_a20 glcd_pclk f4 ptd13 disabled ptd13 spi2_sout sdhc0_d5 fb_a21 glcd_de e5 ptd14 disabled ptd14 spi2_sin sdhc0_d6 fb_a22 glcd_hfs e4 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 fb_a23 glcd_vfs f6 ptf15 disabled ptf15 uart0_rts_b glcd_d11 e1 ptf16 disabled ptf16 spi2_pcs0 ftm0_ch3 uart0_cts_ b/ uart0_col_b glcd_d12 b1 ddr_vdd ddr_vdd ddr_vdd a1 ddr_vss ddr_vss ddr_vss d3 ddr_dqs1 disabled ddr_dqs1 d1 ddr_dq8 disabled ddr_dq8 c1 ddr_dq9 disabled ddr_dq9 b5 ddr_vdd ddr_vdd ddr_vdd a5 ddr_vss ddr_vss ddr_vss d5 ddr_vss ddr_vss ddr_vss c2 ddr_dq10 disabled ddr_dq10 b2 ddr_dq11 disabled ddr_dq11 pinout k70 sub-family data sheet, rev. 4, 10/2012. 92 freescale semiconductor, inc. 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport c3 ddr_dq12 disabled ddr_dq12 b8 ddr_vdd ddr_vdd ddr_vdd a12 ddr_vss ddr_vss ddr_vss c4 ddr_dq13 disabled ddr_dq13 b3 ddr_dq14 disabled ddr_dq14 a2 ddr_dq15 disabled ddr_dq15 a3 ddr_dm1 disabled ddr_dm1 e8 ddr_vss ddr_vss ddr_vss b12 ddr_vdd ddr_vdd ddr_vdd a16 ddr_vss ddr_vss ddr_vss c6 ddr_vref ddr_vref ddr_vref c5 ddr_dq0 disabled ddr_dq0 b4 ddr_dq1 disabled ddr_dq1 a4 ddr_dq2 disabled ddr_dq2 c16 ddr_vdd ddr_vdd ddr_vdd c7 ddr_vss ddr_vss ddr_vss b6 ddr_dq3 disabled ddr_dq3 d6 ddr_dq4 disabled ddr_dq4 a6 ddr_dq5 disabled ddr_dq5 a7 ddr_odt disabled ddr_odt e11 ddr_vss ddr_vss ddr_vss d2 ddr_vdd ddr_vdd ddr_vdd c9 ddr_vss ddr_vss ddr_vss b7 ddr_dq6 disabled ddr_dq6 a8 ddr_dq7 disabled ddr_dq7 c8 ddr_dqs0 disabled ddr_dqs0 d9 ddr_dm0 disabled ddr_dm0 d4 ddr_vdd ddr_vdd ddr_vdd c14 ddr_vss ddr_vss ddr_vss a9 ddr_ba0 disabled ddr_ba0 b10 ddr_ba1 disabled ddr_ba1 b9 ddr_ba2 disabled ddr_ba2 a10 ddr_ckb disabled ddr_ckb a11 ddr_ck disabled ddr_ck d7 ddr_vdd ddr_vdd ddr_vdd d8 ddr_vss ddr_vss ddr_vss d10 ddr_a0 disabled ddr_a0 c11 ddr_a1 disabled ddr_a1 b11 ddr_a2 disabled ddr_a2 c12 ddr_a3 disabled ddr_a3 pinout k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 93 256 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport e10 ddr_vdd ddr_vdd ddr_vdd d12 ddr_vss ddr_vss ddr_vss c10 ddr_a4 disabled ddr_a4 a13 ddr_a5 disabled ddr_a5 a14 ddr_a6 disabled ddr_a6 d11 ddr_a7 disabled ddr_a7 a15 ddr_a8 disabled ddr_a8 e12 ddr_vdd ddr_vdd ddr_vdd e3 ddr_vss ddr_vss ddr_vss b16 ddr_cke disabled ddr_cke b15 ddr_a9 disabled ddr_a9 b13 ddr_a10 disabled ddr_a10 b14 ddr_a11 disabled ddr_a11 c15 ddr_a12 disabled ddr_a12 d16 ddr_a13 disabled ddr_a13 d15 ddr_a14 disabled ddr_a14 e16 ddr_ras_b disabled ddr_ras_b c13 ddr_cas_b disabled ddr_cas_b d14 ddr_cs_b disabled ddr_cs_b d13 ddr_we_b disabled ddr_we_b 8.3 k70 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k70 sub-family data sheet, rev. 4, 10/2012. 94 freescale semiconductor, inc. 1 a ddr_vss b ddr_vdd c ddr_dq9 d ddr_dq8 e ptf16 f ptf17 g ptf18 h ptf19 j pte9 k pte11 l vout33 m usb0_dp n pga2_dp/ p pga3_dp/ r pga0_dp/ 1 t pga1_dp/ 2 ddr_dq15 ddr_dq11 ddr_dq10 ddr_vdd pte0 pte1/ pte3 pte6 pte10 pte17 vss usb0_dm pga2_dm/ pga3_dm/ pga0_dm/ 2 pga1_dm/ 3 ddr_dm1 ddr_dq14 ddr_dq12 ddr_dqs1 ddr_vss pte2/ pte4/ pte7 pte16 pte12 vregin pte19 adc0_se16/ adc1_se16/ dac0_out/ 3 vref_out/ 4 ddr_dq2 ddr_dq1 ddr_dq13 ddr_vdd ptd15 ptd13 pte5 pte8 ptd8 ptd6/ pte18 vrefl vssa vrefh dac1_out/ 4 vss 5 ddr_vss ddr_vdd ddr_dq0 ddr_vss ptd14 ptd12 ptd11 ptf20 ptd5 ptd4/ tamper1 tamper0/ vdda vbat tamper3 5 extal32 6 ddr_dq5 ddr_dq3 ddr_vref ddr_dq4 ptd10 ptf15 ptf14 ptf13 ptd3 ptd2/ tamper2 tamper7 tamper6 tamper4 tamper5 6 xtal32 7 ddr_odt ddr_dq6 ddr_vss ddr_vdd ptd7 ptd9 vdd vddint vdd pte27 pte28 pte26 vss pte24 pte25 7 pta0 8 ddr_dq7 ddr_vdd ddr_dqs0 ddr_vss ddr_vss ptd1 vdd vss vss vss ptd0/ ptc19 pta1 pta3 pta4/ 8 pta2 9 ddr_ba0 ddr_ba2 ddr_vss ddr_dm0 ptc17 ptc16 vdd vss vss vss vss ptc18 ptf22 ptf21 ptf25 9 ptf26 10 ddr_ckb ddr_ba1 ddr_a4 ddr_a0 ddr_vdd ptc15 vdd vddint vdd vdd vdd pta12 pta13/ ptf23 ptf24 10 ptf27 11 ddr_ck ddr_a2 ddr_a1 ddr_a7 ddr_vss ptc9 ptc10 ptc11/ ptc14 ptf11 ptf12 ptb1 pta16 pta15 pta14 11 pta17 12 ddr_vss ddr_vdd ddr_a3 ddr_vss ddr_vdd ptc6/ ptc7 ptc8 ptc12 ptf9 ptf10 ptb0/ pta8 pta7 pta6 12 pta5 13 ddr_a5 ddr_a10 ddr_cas_b ddr_we_b ptc3/ ptc1/ ptb20 ptb17 ptb10 ptc13 ptf1 pta26 pta24 pta10 pta11 13 pta9 14 ddr_a6 ddr_a11 ddr_vss ddr_cs_b ptc4/ ptc2 ptb21 ptb18 ptb11 ptb8 ptb6 ptb3 pta29 pta28 pta25 14 vss 15 ddr_a8 ddr_a9 ddr_a12 ddr_a14 ptc5/ ptf7 ptb22 ptb19 ptb16 ptb9 ptb7 ptb5 ptb4 ptb2 pta27 15 pta18 16 a ddr_vss b ddr_cke c ddr_vdd d ddr_a13 e ddr_ras_b f ptf8 g ptc0 h ptb23 j ptf6 k ptf5 l ptf4 m ptf3 n ptf2 p ptf0 r reset_b 16 t pta19 llwu_p7 llwu_p8 llwu_p9 llwu_p0 llwu_p1 llwu_p10 llwu_p6 llwu_p2 llwu_p11 llwu_p15 llwu_p14 llwu_p13 llwu_p12 rtc_ wakeup_b llwu_p5 cmp1_in2/ adc0_se21 adc2_dp0/ adc3_dp3/ adc0_dp1 adc2_dm0/ adc3_dm3/ adc0_dm1 llwu_p4 cmp2_in2/ adc0_se22 adc3_dm0/ adc2_dm3/ adc1_dm1 adc3_dp0/ adc2_dp3/ adc1_dp1 llwu_p3 cmp0_in4/ cmp2_in3/ adc1_se23 cmp1_in3/ adc0_se23 adc0_dm0/ adc1_dm3 adc0_dp0/ adc1_dp3 adc1_dm0/ adc0_dm3 cmp1_in5/ cmp0_in5/ adc1_se18 adc1_dp0/ adc0_dp3 figure 46. k70 256 mapbga pinout diagram 9 revision history the following table provides a revision history for this document. revision history k70 sub-family data sheet, rev. 4, 10/2012. freescale semiconductor, inc. 95 table 62. revision history rev. no. date substantial changes 3 3/2012 initial public release 4 10/2012 replaced tbds throughout. revision history k70 sub-family data sheet, rev. 4, 10/2012. 96 freescale semiconductor, inc. how to reach us: hoe ae: wwweescaeco e ot: htt:wwweescaecosot uoe o ocatos ot ste: eescae ecocto echca oato ete ast ot roa ee oa o wwweescaecosot oe e ast a ca: eescae haete etscha h echca oato ete chatoe eche ea sh sh ea ech wwweescaecosot aa: eescae ecocto aa t heaates r owe hoeo eo oo aa o sotaaeescaeco saacc: eescae ecocto ha t chae o ao roa haoa stct e ha sotasaeescaeco ocet e: re oato ths ocet s oe soe to eae sste a sotwae eetes to se eescae ecoctos octs hee ae o eess o e coht ceses ate heee to es o acate a teate ccts o teate ccts ase o the oato ths ocet eescae ecocto esees the ht to ae chaes wthot the otce to a octs hee eescae ecocto aes o waat eesetato o aatee ea the stat o ts octs o a atca ose o oes eescae ecocto asse a at as ot o the acato o se o a oct o cct a secca scas a at c wthot tato coseeta o ceta aaes ca aaetes that a e oe eescae ecocto ata sheets ao seccatos ca a o a eet acatos a acta eoace a a oe te oeat aaetes c cas st e aate o each cstoe acato cstoes techca eets eescae ecocto oes ot coe a cese e ts atet hts o the hts o othes eescae ecocto octs ae ot ese tee o athoe o se as cooets sstes tee o sca at to the o o othe acatos tee to sot o ssta e o o a othe acato whch ae o the eescae ecocto oct co ceate a stato whee esoa o eath a occ ho e chase o se eescae ecocto octs o a sch tee o athoe acato e sha e eescae ecocto a ts oces eoees ssaes aates a sttos haess aast a cas costs aaes a eeses a easoae attoe ees as ot o ect o ect a ca o esoa o eath assocate wth sch tee o athoe se ee sch cas aees that eescae ecocto was eet ea the es o aacte o the at rohcoat ao ee esos o eescae octs hae the ctoat a eectca chaactestcs as the orohcoat ao oee coteats o the oato see htt:wwweescaeco o cotact o eescae saes eesetate o oato o eescaes oeta octs oa o to htt:wwweescaecoe eescae a the eescae oo ae taeas o eescae ecocto c othe oct o sece aes ae the oet o the esecte owes eescae ecocto c |
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